1. Field of the Invention
The present application relates generally to an improved data processing system, and in particular to a multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases.
2. Description of the Related Art
Multiple processor systems are generally known in the art. In a multiple processor system, a process may be shared by a plurality of processors. The process is broken up into threads which may be processed concurrently. The threads must be queued for each of the processors of the multiple processor system before they may be executed by a processor. Some processors are capable of processing multiple threads simultaneously. These processors are referred to as Simultaneous Multi-Threaded (SMT) processors. SMT provides significant increases in microprocessor throughput by issuing instructions from multiple threads per clock cycle. Instructions may be executed in-order or out-of-order. In-order execution is the ability to execute instructions in program order. For in-order execution mode, if a first instruction depends on the result of a second instruction, the processor cannot issue the first instruction until the processor knows the result of the second instruction. The processor then issues the second instruction after the processor issues the first instruction. Out-of-order execution is the ability to execute instructions not necessarily in program order, but rather as soon as an instruction's input operands are available to enable an increase in processor performance. For example, in out-of-order execution mode, the processor jumps to the next instruction that does not depend on the result of a previous instruction and issues this non-dependent instruction.
A common technique used when designing SMT processors is register renaming. Registers are temporary storage places which a central processing unit (CPU) uses to store the variables (values) of an instruction. Register renaming addresses the name dependencies which may occur in out-of-order execution mode, and avoids unnecessary serialization of program operations imposed by reuse of registers by those operations. For example, when two instructions use the same register, renaming the register for one of the instructions allows the two instructions to execute simultaneously or be reordered without conflict. Thus, register renaming changes the name of a register to the name of an available register, and then assigns data to the available register.
Thus, register renaming allows for increasing processor performance by allowing instructions to execute out-of-order. However, as the number of threads that may be executed in an SMT microprocessor increases, the performance gain due to out-of-order execution drops significantly. For instance, when the number of threads approaches 4-way SMT or 8-way SMT, most of the performance gain that may be achieved by increasing throughput using out-of-order execution is negated by the number of instructions issued from the other threads. Additional threads also require more architected registers, which in turn require more silicon overhead.